In recent years, research and development are being conducted on a nonvolatile variable resistance memory device (hereafter also simply referred to as “nonvolatile memory device”) having a memory cell that includes a nonvolatile variable resistance memory element (hereafter also simply referred to as “variable resistance element”). The variable resistance element is such an element that has at least two threshold voltages (a threshold voltage for writing and a threshold voltage for erasing), reversibly changes in resistance value by an electrical signal exceeding the writing or erasing threshold voltage, and enables data corresponding to the resistance value to be written in a nonvolatile manner.
As a nonvolatile memory device using such a variable resistance element, the following nonvolatile memory device is typically known. In the nonvolatile memory device, 1T1R memory cells in each of which a MOS transistor and a variable resistance element are connected in series with each other are arrayed in a matrix at crosspoints of orthogonally arranged bit lines and word lines with source lines (the source lines are in parallel with either the bit lines or the word lines).
PTL 1 describes a nonvolatile memory device including 1T1R memory cells in each of which a variable resistance element has a memory layer formed using an amorphous thin film such as a rare-earth oxide film.
FIG. 32 is a diagram showing a structure of a memory cell described in PTL 1.
A memory cell 1001 is formed by electrically connecting a variable resistance element 1002 and a MIS transistor 1003 as an active element for controlling access to the variable resistance element 1002, in series with each other.
The variable resistance element 1002 has a memory layer 1002c sandwiched between a first electrode 1002a and a second electrode 1002b. 
As a material used for the memory layer 1002c, a material obtained by containing an easily ionizable metal such as Cu, Ag, or Zn in a rare-earth oxide film is disclosed.
As shown in FIG. 32, voltage application to the memory cell 1001 is performed as follows. A terminal voltage V1 is applied to a terminal of the variable resistance element 1002 opposite to a terminal connected to the MIS transistor 1003. A terminal voltage V2 is applied to a terminal (for example, a source terminal) of the MIS transistor 1003 opposite to a terminal connected to the variable resistance element 1002. A gate voltage Vgs is applied to a gate of the MIS transistor 1003.
By applying the terminal voltages V1 and V2 respectively to these ends of the variable resistance element 1002 and the MIS transistor 1003 constituting the memory cell 1001, a potential difference V (=|V2−V1|) is created across both terminals.
As a method of writing to the memory cell 1001, a bipolar resistance change operation is disclosed. That is, when the variable resistance element 1002 is in a high resistance state, the gate of the MIS transistor 1003 is turned ON and the voltage V (=|V2−V1|) is applied across both terminals of the memory cell 1001. In the case where the voltage across both ends of the variable resistance element 1002 exceeds the above-mentioned writing threshold voltage of the variable resistance element 1002, the variable resistance element 1002 decreases in resistance value and changes from the high resistance state to a low resistance state. When the variable resistance element 1002 is in the low resistance state, the gate of the MIS transistor 1003 is turned ON and the voltage V opposite in polarity to that in the writing step is applied across the variable resistance element 1002 and the MIS transistor 1003 in the memory cell 1001. In the case where the voltage across both ends of the variable resistance element 1002 exceeds the above-mentioned erasing threshold voltage of the variable resistance element 1002, the variable resistance element 1002 increases in resistance value and changes from the low resistance state to the high resistance state.
As shown in FIG. 33, in the change of the variable resistance element 1002 from the high resistance state to the low resistance state, the resistance value of the variable resistance element 1002 is determined by a current-voltage operating point of the series connected variable resistance element 1002 and MIS transistor 1003. This value is determined by a current value flowing when the voltage of the variable resistance element 1002 becomes the writing threshold voltage (denoted by Vth).
Accordingly, the resistance value of the variable resistance element 1002 in the low resistance state can be controlled by the gate voltage of the MIS transistor 1003. In FIG. 33, by changing the gate voltage to VG3, VG2, and VG1, the operating point near the threshold voltage Vth is changed to P3, P2, and P1, so that the resistance value of the variable resistance element 1002 can be arbitrarily set to be lower (larger in current) in this order. This property is utilized to provide a multi-value memory device capable of recording information of three values or more.
PTL 2 describes a nonvolatile memory device including 1T1R memory cells in each of which a variable resistance element comprises a strongly-correlated electron oxide.
FIG. 34 is a diagram showing a structure of a memory cell described in PTL 2.
A memory cell 1140 is formed by electrically connecting a variable resistance element 1130 and a MOS transistor 1138 as an active element for controlling access to the variable resistance element 1130, in series with each other.
The variable resistance element 1130 has a variable resistance layer 1134 sandwiched between a first electrode 1136 and a second electrode 1132.
As a material used for each component, titanium (Ti) for the first electrode 1136, copper (Cu) for the second electrode 1132, and copper oxide (CuO) for the variable resistance layer 1134 are disclosed.
As a method of writing to the memory cell 1140, when the variable resistance element 1130 is in the high resistance state, one of drain and source terminals of the MOS transistor 1138 (for example, the source terminal) not connected to the variable resistance element 1130 is set to a reference voltage (ground), and a positive voltage is applied to the first electrode 1136 so that a programming voltage Vpg is applied to the variable resistance element 1130. This causes the variable resistance element 1130 to change from the high resistance state to the low resistance state, as a result of which the memory cell 1140 becomes the low resistance state.
On the other hand, when the variable resistance element 1130 is in the low resistance state, an erasing voltage Ver causing a current to flow from the second electrode 1132 to the first electrode 1136 is applied to the variable resistance element 1130. This causes the variable resistance element 1130 to change from the low resistance state to the high resistance state, as a result of which the memory cell 1140 becomes the high resistance state.
It is also disclosed that the resistance value of the memory cell 1140 in the low resistance state is determined in inverse proportion to the voltage of the gate G or the programming voltage Vpg in the programming step mentioned above. That is, the resistance value of the memory cell 1140 shifts to a lower value when the voltage of the gate G or the programming voltage Vpg increases.
Hence, a low resistance value adjustment unit that detects a resistance level and, in the case where writing to the low resistance state is insufficient, performs adjustment by decreasing the write level while increasing the write voltage is disclosed in PTL 2.
FIG. 35(a) is a flowchart for adjusting the resistance value while increasing the applied voltage of the upper electrode 1136, and FIG. 35(b) is a flowchart for adjusting the resistance value while increasing the applied voltage of the gate G of the transistor 1138.
PTL 1 discloses applications to multi-value memory devices. According to the disclosure, even in the case of applying to a two-value memory of the low resistance state and the high resistance state, variations in current capability caused by variations in transistor manufacturing process appear as variations in low resistance value.
Such variations in low resistance value can be effectively suppressed by the adjustment unit in PTL 2 that adjusts the resistance level while successively increasing the same-polarity voltage in low resistance writing.
In a memory device that utilizes a resistance change of a memory cell for writing data, data discrimination reliability is enhanced by separating, with a margin, a distribution difference between the high resistance state and the low resistance state of a large number of memory cells. Moreover, a reading speed of the memory device is generally based on a worst value of a memory cell through which a large cell current flows (a memory cell in the low resistance state). Accordingly, by lowering an upper limit of the low resistance value in the variable resistance memory, a higher speed can be attained. Hence, it is very important to set the cell current of the memory cell in the low resistance state, to a specified value or more.